设为首页 设为首页 加入收藏 加入收藏 网站地图
[请登陆][免费注册]
搜 索

您的位置 :首页  新闻产业观察
克服大批量生产的薄片检测挑战
                   0
出自:SEMI中国

By Philippe Gastaldo, Product and R&D Director, UnitySC
 
As the automotive electronics market continues to grow, spurred by developments such as semi-autonomous and fully autonomous vehicles, the demand is increasing for power semiconductor components with sophisticated conversion schemes that decrease power consumption and heat. To address these needs, power semiconductor manufacturers are turning to thin wafers.
 
Today’s power semiconductors are manufactured primarily on 200mm wafers that range in thickness from 50 to 100μm, but their roadmaps are targeting wafers as thin as 1μm. These wafers are thinned on the backside by mechanical polishing. Defects resulting from the polishing process include grinding marks, grinding failures resulting in edge chips, star cracks and comets formed by edge particles that get caught in the grinding wheel, embedded particles, cleavage lines and a variety of other imperfections.
 
Because these defects often appear on the wafer backside rather than the active side, they are not as much of an issue for thicker wafers. But as wafers become increasingly thinner, these defects are affecting chip reliability. While the backside defects in thinned wafers don’t initially impede the chip’s functionality, they do impact the device’s overall reliability. In fact, a power semiconductor can easily be processed through to final packaging without detecting the defects. However, when subjected to the high temperatures of an automotive application, for example, a crack can form and lead to chip failure.
 
While thin-wafer inspection has become critically important for the wafer-sorting process, as well as helping engineers improve thinning processes themselves, many of the existing technologies are limited and inadequate for detecting defects.
 
Most of today’s defect inspection is done manually, by visual inspection, using a powerful light, but without magnification. As this process is often performed by different operators, it’s not repeatable, and results in minimal defect information that lacks accurate classification.
 
Automated optical inspection that uses a camera with magnification has also been tried, without success, because while it provides an automated and repeatable process, it is not capable of inspecting the wafer topography to distinguish between grinding marks and deep cracks.
 
Some have considered darkfield inspection an option for detecting defects in thin wafers. Based on optical technology, darkfield is the measurement of light reflected at a lower angle. While darkfield is useful for front-end inspection, backside grinding renders it ineffective due to the resulting wafer-surface roughness. As a result, darkfield inspection should be avoided following backside grinding.
 
Optimal thin-wafer inspection requires a technology that is sensitive to nanotopography and that can both detect and measure surface variations of nanometric proportions. Interferometry, a measurement method using the phenomenon of interference of light, radio or sound waves1, is capable of this, but many tools based on interferometry are slow and expensive with low throughput. Additionally, while interferometry is an excellent option for some surface inspection applications, it is not suitable for inspecting and sorting thin wafers in a high-volume manufacturing environment.
 
Alternatively, there is a technology known as phase-shift deflectometry (PSD) that measures the wafer surface topography by imaging through the surface and generating a pattern on the tool display. Topography variation on the surface changes the shape of the pattern, which indicates the presence of a defect. By generating images of the topography map, pitch analysis can be performed to accurately classify the defect while providing its size and depth. Used until recently for Silicon on Insulator (SOI) and Epitaxial (EPI) wafer inspection and slip line detection, PSD is gaining traction for wafer thinning inspection.
 
Companies that work with ultra-thin wafers are beginning to employ PSD technology that is both cost-effective and fast enough for high-volume manufacturing. Additionally, some companies are beginning to integrate automatic classification software that provides accurate and detailed defect information. This approach, with its advantages over the predominant visual inspection currently being employed by most manufacturers, is expected to become the preferred method for thin-wafer inspection—particularly in power semiconductor applications for mission-critical applications like automotive. UnitySC is pioneering this approach with its 4See Series and Deflector module.

 

 

0
                   0
文章收入时间: 2017-09-20
相关信息
专为智能汽车打造 首个国家级自动驾驶测试场正式启用 2018-02-23
各家人工智能芯片齐头并进 这是AI手机爆发的前奏 2018-02-23
IC设计也用上AI,帮助降低工艺演进引发的成本问题 2018-02-23
中国抢下人工智能先手棋:位列全球第一梯队 或迎洗牌 2018-02-23
谷歌让AI决定广告数量和位置:助站长收入提升10% 2018-02-23
英特尔携手紫光展锐启动5G战略合作 2018-02-23
我国半导体量子芯片研究获突破:首次实现三量子比特逻辑门 2018-02-23
华为自家海思芯片今年将投入大规模量产 2018-02-23
总投资108亿 华灿光电拟在义乌投建先进半导体与器件项目 2018-02-23
英特尔计划未来三年在以色列投资50亿美元 2018-02-23
 
SEMI简介 | About SEMI | 联系我们 | Privacy Policy | semi.org
上海集成电路协会 | 中国电子报 | 赛迪网半导体 | 电子产品世界 | 中电网 | 中国电子材料网
Copyright © 2017 SEMI®. All rights reserved.
沪ICP备06022522号
沪公网安备31011502000679号